Calculation of Power Consumption in 7 Transistor Sram Cell Using Cadence Tool
نویسندگان
چکیده
In this paper a new 7T SRAM is proposed. CMOS SRAM Cell is very less power consuming and have very less read and write time. In proposed SRAM an additional write bit line balancing circuitry is added in 6T SRAM for power reduction. A seven Transistor (7T) cell at 45 nm Technology is proposed to accomplish improvement in stability, power dissipation and performance compared with previous designs. Simulation result of proposed design using CADENCE TOOL shows the reduction in total average power consumption.
منابع مشابه
Design of Low Power Robust Symmetric Sram Cell Using Gated Ground Technique
Memory is an important part of any electronic device. In today's world static random access memory (SRAM) is widely used as memory. The major issues for design of SRAM are power loss, delay and stability. This paper presents a modified form of a symmetric eight-transistor SRAM bit-cell. In this paper transmission gate has been used as access transistor which provides rail-to-rail swing. Moreove...
متن کاملAnalysis of Leakage Power Reduction in 6T SRAM Cell
On chip cache memories contributes a large fraction to the total power consumption of microprocessor. As technology scales down into d e e p -submicron, leakage power is becoming a dominant source of power consumption. As cache memory is an array structure leakage reduction in just one memory cell can on the whole reduce a large amount of leakage power. In this thesis leakage power of conventio...
متن کاملA Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability
This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...
متن کاملHigh Density Four-transistor Sram Cell with Low Power Consumption
This paper presents a CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. The new cell size is 35.45% smaller than a conventional sixtransistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform...
متن کاملDesign of a Low Power 10T SRAM Cell
SRAM is a semiconductor memory cell. In this paper, a 10T SRAM cell is designed by using cadence virtuoso tool in 180nm CMOS technology. Its performance characteristics such as power, delay, and power delay product are analysed. 10T SRAM cell is basically 6T SRAM cell with 4 extra transistors. In this 10T SRAM cell, additional read circuitry is attached to avoid flipping of cell. The power diss...
متن کامل